• DocumentCode
    1704969
  • Title

    FPGA implementation of a multi-channel HDLC protocol transceiver

  • Author

    Zhen-Bin, Gao ; Jian-fei, Liu

  • Author_Institution
    Sch. of Inf. Eng., Hebei Univ. of Technol., Tianjin, China
  • Volume
    2
  • fYear
    2005
  • Lastpage
    1302
  • Abstract
    An HDLC protocol transceiver was designed, which contains two full-duplex channels, a build-up 4K-bytes dual-port RAM and an interrupt management unit. Based on the principle of top-down design, the VHDL modeling of the main modules, such as transmitter, receiver, and memory management unit were discussed. The design was implemented in a Virtex FPGA. It is simple, flexible, and easy to use.
  • Keywords
    field programmable gate arrays; hardware description languages; interrupts; protocols; random-access storage; transceivers; VHDL modeling; Virtex FPGA; dual-port RAM; full-duplex channels; interrupt management unit; multi-channel HDLC protocol transceiver; receiver; top-down design; transmitter; Automatic control; Control systems; Field programmable gate arrays; Protocols; Random access memory; Read-write memory; Registers; Silicon carbide; Transceivers; Transmitters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications, Circuits and Systems, 2005. Proceedings. 2005 International Conference on
  • Print_ISBN
    0-7803-9015-6
  • Type

    conf

  • DOI
    10.1109/ICCCAS.2005.1495345
  • Filename
    1495345
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1704969