DocumentCode :
1705015
Title :
A timing-and-area tradeoff GF(p) elliptic curve processor architecture for FPGA
Author :
Shuhua, Wu ; Yuefei, Zhu
Author_Institution :
Dept. of Networks Eng., Zhengzhou Inf. Eng. Univ., China
Volume :
2
fYear :
2005
Lastpage :
1312
Abstract :
This paper presents a timing-and-area tradeoff elliptic curve processor architecture which can compute point multiplication with an arbitrary point on an elliptic curve over the field GF(p) (where p is any 192-bit prime integer) in 6.0 ms using relatively fewer resources. The Montgomery modular multiplication is optimized for the elliptic curve processor by avoiding the final comparison. All the other field arithmetic operations involved are performed efficiently also with no comparison by mostly exploiting the features of the arithmetic unit to deliver well-pipelined computations. Furthermore, an efficient method, called the decomposition and composition of a finite state machine, is adopted in this paper to design the controllers of the elliptic curve processor.
Keywords :
Galois fields; controllers; cryptography; field programmable gate arrays; finite state machines; pipeline arithmetic; FPGA; GF(p) elliptic curve processor architecture; Montgomery modular multiplication; arithmetic unit; composition; controllers; decomposition; finite state machine; point multiplication; timing-and-area tradeoff; well-pipelined computations; Arithmetic; Automata; Computational efficiency; Computer architecture; Design methodology; Elliptic curve cryptography; Elliptic curves; Field programmable gate arrays; Hardware; Partial response channels;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Circuits and Systems, 2005. Proceedings. 2005 International Conference on
Print_ISBN :
0-7803-9015-6
Type :
conf
DOI :
10.1109/ICCCAS.2005.1495347
Filename :
1495347
Link To Document :
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