Design the efficient block digital filters for calibration of timing-error effects in time-interleaved ADC system

This paper considers the problem of efficient block digital filter (BDF) design for calibrating timing-errors in a time-interleaved analog-to-digital converter (TIADC) system. The traditional calibrating filters can not achieve the throughout rate that the TIADC needs. This paper first brings the block digital filters for calibration of the timing-errors in the TIADC. The different BDF design methods were proposed due to the different number of TIADC channels. The proposed block digital filters can increase the parallelism of the computation and can greatly reduce the high clock speed that TIADC needs.