Low power adiabatic logic circuits with feedback structure using three-phase power supply

Non-adiabatic energy loss is the main source of power consumption in adiabatic circuits. This paper presents an approach to eliminate the non-adiabatic energy loss on output nodes to realize power-efficient design. The total power consumption of the proposed circuits is significantly reduced, as the energy transferred to output nodes is mostly recovered by using feedback control from next-stage or current-stage buffer in a pipelined structure. A 16-bit carry-lookahead adder is verified. A three-phase power-clock generator is also suggested. HSPICE simulation results indicate that the proposed adder consumes only 30% of the dissipated energy of a 2N-2N2P one and is about 50 % of the dissipated energy of a PAL-2N one for clock rates ranging from 50 to 200 MHz.