A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS

Author

Tohidian, Massoud ; Madadi, Iman ; Staszewski, Robert Bogdan

Author_Institution

Delft Univ. of Technol., Delft, Netherlands

fYear

2013

Firstpage

174

Lastpage

175

Abstract

Filters are key building blocks in wireless communication and analog signal processing. Typically, Gm-C and active-RC topologies are being used for this purpose. However, reduced supply voltage and lower transistor output impedance make it difficult to implement high-gain wide-bandwidth opamps in a power-efficient manner. Moreover, portable wireless communication devices demand nowadays ever decreasing power consumption, and more tunability/reprogrammability. A discrete-time (DT) analog signal processing approach appears to answer these requirements.

Keywords

CMOS digital integrated circuits; IIR filters; RC circuits; band-stop filters; signal processing; 7th-order discrete-time IIR filter; DT analog signal processing approach; Gm-C topologies; active-RC topologies; bandwidth 400 kHz to 30 MHz; discrete-time analog signal processing approach; high-gain wide-bandwidth opamps; portable wireless communication devices; power 2 mW; power consumption; size 65 nm; stop-band rejection; transistor output impedance;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4673-4515-6

Type

conf

DOI

10.1109/ISSCC.2013.6487687

Filename

6487687