A fault-tolerant SDRAM controller based on a dynamically reconfigurable shift register chain

A SDRAM like conventional memories can be affected by the occurrence of single event upsets (SEUs) which can lead to serious faults such as single-bit error. In order to cope with this effect of SEUs, a fault-tolerant SDRAM controller is proposed instead of previous approaches that required modifications to the internal structure of the SDRAM itself. For one thing, an optimized encoder and decoder based the (40, 32) Hamming code are integrated to eliminate the problem of single-bit error. Moreover, in the context of error correction, a write request shift register chain is adopted to prefetch the subsequence write requests, and simultaneously a data correction shift register chain is applied to hide the delay of write-back into the following accesses. Besides, with the dynamic combination of two chains, a reconfigurable new chain can be generated to achieve the goal that the burst read data, corrected data and requested write data can be issued seamlessly. Simulation results show that, the optimized encoder and decoder reduce 16.45% area overhead with the slight delay, and the proposed structure could also reduce 11.2% execution time of the test program.