A fully differential high-speed double-edge triggered flip-flop (DETFF)

Author

Sameni, Pedram ; Mirabbasi, Shahriar

Author_Institution

Dept. of Electr. & Comput. Eng., British Columbia Univ., Canada

Volume

3

fYear

2004

Firstpage

1459

Abstract

A high-speed double-edge-triggered flip-flop designed in 0.18 μm CMOS technology is presented. Flip-flops, to a large extent, determine the speed of synchronous systems. The proposed flip-flop can operate with a clock rate as high as 12.5 GHz, which translates to 25 Gb/s data rate. It samples the data on both edges of the clock. All signals are realized differentially. The differential output swing is 0.8 V with a 1.8 V power supply. The average power consumption is 7 mW. A performance comparison between the proposed flip-flop and a single-edge triggered flip-flop realized in the same technology is also presented.

Keywords

CMOS digital integrated circuits; flip-flops; high-speed integrated circuits; integrated circuit design; power consumption; 0.18 micron; 0.8 V; 1.8 V; 25 Gbit/s; 7 mW; CMOS technology; clock rate; data rate; differential flip-flop; differential high-speed double-edge triggered flip-flop; differential output swing; high-speed flip-flop; CMOS technology; Clocks; Data processing; Energy consumption; Flip-flops; Integrated circuit technology; Latches; Multiplexing; Power supplies; System performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2004. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-8253-6

Type

conf

DOI

10.1109/CCECE.2004.1349679

Filename

1349679