Title :
A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems
Author :
Qazi, M. ; Amerasekera, A. ; Chandrakasan, Anantha P.
Author_Institution :
Massachusetts Inst. of Technol., Cambridge, MA, USA
Abstract :
Nonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy [1] and high-performance systems managing power by operating “normally off” [2]. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data.
Keywords :
CMOS logic circuits; CMOS memory circuits; application specific integrated circuits; capacitors; ferroelectric storage; logic design; random-access storage; ASIC design flow; CMOS process; FeRAM-enabled D flip-flop; NVDFF; NVDFF statistical signal margin; PMU; detection circuitry; digital circuit; digital systems; embedded ferroelectric capacitors; energy cost; information processing; nonvolatile D flip-flop design; nonvolatile processing; portable electronics; power management unit; Field effect transistors; Finite impulse response filters; Flip-flops; Latches; Nonvolatile memory; Phasor measurement units; Sensors;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487695
