Discussion on parameters setting and loss of exciter time constant compensation in excitation system

This paper develops a self-design model of automatic voltage regulator (AVR) with criteria of performance indices recommended in IEEE Std 421.5. During the control parameters design and model simulation phase, we can verify all performance indices to see if they meet the specification, such as the steady state error in time domain, phase margin, and the zero crossover frequency in frequency domain, etc. So it is easy to create a full design procedure step by step deterministically. In the voltage constant mode of the excitation control system of a synchronous generator, there is an exciter time constant compensation function to reduce the effective exciter field time constant and increase the small signal response bandwidth. The exciter time constant compensation consists essentially of a direct negative feedback around the exciter with signal coming from exciter field current (I_fe). However, it is the main control loop in field constant mode of excitation system. In a traditional analog-based or in a modern digital-based excitation system, loss of exciter time constant compensation is a failure to cause generator terminal voltage unstable. The deteriorated phase margin will impact on power system stability maybe, or result in unit trip unexpectedly. From the point of operation risk assessment and management, we still have to evaluate stability margin in the design phase. This paper suggests that this failure mode should be taken into design consideration besides small signal performance indices. A simple way to resolve the stability margin is to restore the loop forward gain K₂ properly to improve the phase margin. It is also necessary to offer a standard operation procedure (SOP) for operators to follow after loss of exciter time constant.