Title :
A closer look at multiple faults and defect levels in digital circuits
Author_Institution :
Norwegian Inst. of Technol., Trondheim, Norway
Abstract :
The defect level versus production yield and fault coverage of test programs for VLSI chips is investigated. The focus is on low yield, for which multiple faults are dominant. Various multiple fault coverage models are presented, and the importance of choosing an accurate model for multiple fault coverage is demonstrated. Finally, fault simulation results are presented. Single, double, and triple fault coverages are calculated and compared against the theoretical models
Keywords :
VLSI; digital integrated circuits; fault location; integrated circuit testing; VLSI; defect levels; digital circuits; fault coverage; fault simulation; multiple faults; production yield; test programs; Circuit faults; Circuit testing; Digital circuits; Distribution functions; Electrical fault detection; Fault detection; Integrated circuit measurements; Production; Semiconductor device measurement; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.14959
