Title :
A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology
Author :
Tz-yi Liu ; Tian Hong Yan ; Scheuerlein, R. ; Yingchang Chen ; Lee, Jung Keun ; Balakrishnan, Ganesh ; Yee, G. ; Zhang, Haijun ; Yap, A. ; Ouyang, Jun ; Sasaki, T. ; Addepalli, Sateesh ; Al-Shamma, Ali ; Chin-Yu Chen ; Gupta, Madhu ; Hilton, Gene ; Joshi,
Author_Institution :
Sandisk, Milpitas, CA, USA
Abstract :
ReRAM has been considered as one of the potential technologies for the next-generation nonvolatile memory, given its fast access speed, high reliability, and multi-level capability. Multiple-layered architectures have been used for several megabit test-chips and memory macros [1-3]. This paper presents a MeOx-based 32Gb ReRAM test chip developed in 24nm technology.
Keywords :
integrated circuit reliability; random-access storage; MeOx-based ReRAM test chip; multiple-layered architectures; next-generation nonvolatile memory; reliability; size 24 nm; storage capacity 32 Gbit; two layer ReRAM memory device; Arrays; Charge pumps; Clocks; Leakage currents; Temperature sensors;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487703
