DSP/FPGA implementation of a phase locked loop for digital power electronics

This paper examines the implementation of a Phase Locked Loop (PLL) for obtaining the phase angle information of three-phase grid. The paper compares techniques previously employed to implement the PLL and provides their merits and demerits. A bang-bang type PLL has been designed and implemented in a Digital Signal Processor (DSP) so as to ensure that the PLL continues to function during severe grid conditions. Experimental results have been presented for various cases to verify the theory.