A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs

Author

Kachris, C. ; Sirakoulis, G.C. ; Soudris, D.

Author_Institution

Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece

fYear

2014

fDate

28-29 Oct. 2014

Firstpage

1

Lastpage

6

Abstract

Phoenix MapReduce is a programming framework for multi-core systems that is used to automatically parallelize and schedule the programs based on the MapReduce framework. This paper presents a novel reconfigurable MapReduce accelerator that can be augmented to multi-core SoCs and it can speedup the indexing and the processing of the MapReduce key-value pairs. The proposed architecture is implemented, mapped and evaluated to an all-programmable SoC with two embedded ARM cores (Zynq FPGA). Depending on the MapReduce application requirements, the user can dynamically reconfigure the FPGA with the appropriate version of the MapReduce accelerator. The performance evaluation shows that the proposed scheme can achieve up to 2.3x overall performance improvement in MapReduce applications.

Keywords

electronic engineering computing; field programmable gate arrays; multiprocessing systems; performance evaluation; programming; system-on-chip; ARM core; MapReduce key-value pair processing; Phoenix MapReduce; Zynq FPGA; field programmable gate array; multicore all-programmable SoC; multicore system; performance evaluation; program parallelization; program scheduling; programming framework; reconfigurable MapReduce accelerator; system-on-chip; Acceleration; Field programmable gate arrays; Hardware; Program processors; Programming; Random access memory; System-on-chip; MapReduce; Multi-core programming; scratchpad memory;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip (SoC), 2014 International Symposium on

Conference_Location

Tampere

Type

conf

DOI

10.1109/ISSOC.2014.6972430

Filename

6972430