L2_ISA++: Instruction set architecture extensions for 4G and LTE-advanced MPSoCs

High throughput and low latencies are essential for mobile communication systems. In recent years, particularly the physical layer implementation and its optimization have been focused on. As the bitrates of the physical layer increase, the upper layers of the protocol stack must keep pace with these increased data rates. This can be achieved in two ways. Apart from software optimizations for given hardware, the processor itself can be improved. In this paper, the processing performance of the 4G and LTE-Advanced layer 2 protocol stack of cellular communication systems is dramatically improved. In our approach, a processor is extended with a newly developed application-specific instruction set, called L2_ISA++. Each component of the 4G and LTE-Advanced layer 2 is profiled and analyzed. Afterwards, new instructions are iteratively developed and attached to increase processing performance. Experimental results show a processing performance increase of 50x compared with a RISC-based approach. The uplink as well as the downlink throughput is more than 2.5 Gbit/s for a single processor instance with a clock frequency of 500 MHz. Moreover, the processor with the newly developed instruction set L2_ISA++ is 12x energy efficient compared to the basic RISC core. Consequently, battery powered devices will especially benefit from our approach and an integration in heterogeneous MPSoCs for multi-gigabit data rates becomes feasible.