Title :
A 100 MHz-1GHz on-chip-programmable phase-locked loop
Author :
Vahedi, Haleh ; Shoval, Ayal ; Raahemifar, Kaamran
Author_Institution :
Ryerson Univ., Toronto, Ont., Canada
Abstract :
A programmable wide-range PLL has been designed in the digital subset of TSMC 3.3V, 0.25μ technology that can provide 100-MHz to 1-GHz rail-to-rail digital clock signal from a 50-MHz reference clock. The architecture is appropriate for low-power design. The system is robust against temperature changes so that the stability of the system is guaranteed. Because of the differential configuration of the sub-blocks and using a voltage-controlled oscillator with a low gain and a linear transfer function the system has an acceptable noise rejection.
Keywords :
circuit stability; low-power electronics; phase locked loops; transfer functions; voltage-controlled oscillators; 0.25 micron; 100 MHz to 1 GHz; 3.3 V; 50 MHz; TSMC; differential sub-block configuration; linear transfer function; low-power design; noise rejection; on-chip-programmable PLL; phase-locked loop; stability; voltage-controlled oscillator; wide-range PLL; Automatic control; Clocks; Delay; Logic circuits; Phase frequency detector; Phase locked loops; Threshold voltage; Transfer functions; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Electrical and Computer Engineering, 2004. Canadian Conference on
Print_ISBN :
0-7803-8253-6
DOI :
10.1109/CCECE.2004.1349715
