Title :
Self-timed full adder designs based on hybrid input encoding
Author :
Balasubramanian, P. ; Edwards, D.A. ; Brej, C.
Author_Institution :
Sch. of Comput. Sci., Univ. of Manchester, Manchester
Abstract :
Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are described in this paper. While one of the adder designs incorporates redundancy into the logic, the other design does not. Comparisons have been carried out with respect to various self-timed full adder designs which employ only a single widely used delay-insensitive input encoding for both the inputs and outputs. It has been found out from exhaustive simulations that incorporating redundancy into the logic actually benefits in terms of delay, but a non-redundant implementation proves to be beneficial with respect to power and area parameters.
Keywords :
adders; logic design; commercial synchronous resource; delay insensitive code; hybrid input encoding; self timed full adder; Adders; Circuits; Computer science; Delay; Electronic design automation and methodology; Encoding; Logic design; Protocols; Robustness; Wires;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on
Conference_Location :
Liberec
Print_ISBN :
978-1-4244-3341-4
Electronic_ISBN :
978-1-4244-3340-7
DOI :
10.1109/DDECS.2009.5012099