Title :
Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS
Author :
Seongjong Kim ; Inyong Kwon ; Fick, David ; Myungbo Kim ; Yen-Po Chen ; Sylvester, Dennis
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
Advanced CMOS technologies are highly susceptible to process, voltage, and temperature (PVT) variations due to sub-wavelength lithography and other manufacturing challenges. These variations cause performance uncertainty for which timing margins must be added to guarantee correct operation. Ultimately, this results in lost performance or energy: performance is lost directly through reduced clock frequency, while energy is sacrificed by operating at a higher voltage than necessary to meet non-margined timing requirements.
Keywords :
CMOS integrated circuits; clocks; error detection; lithography; silicon-on-insulator; timing circuits; PVT variation; Razor-lite; SOI CMOS; advanced CMOS technology; clock frequency; nonmargined timing requirement; performance uncertainty; process voltage and temperature vatiation; side-channel error-detection register; size 45 nm; subwavelength lithography; timing margin; timing-margin recovery; Clocks; Delays; Monitoring; Program processors; Rails; Registers;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487728
