Deep-submicron CMOS design of high-performance low-power flash/folding analog-to-digital converters

Author

Liobe, John ; Margala, Martin

Author_Institution

Electr. & Comput. Eng. Dept., Univ. ofRochester, Rochester, NY, USA

Volume

3

fYear

2004

Firstpage

1629

Abstract

High speed embedded ADC designs are a fundamental component of mobile applications. However, low-power and low-voltage constraints, as well as fast conversion rates are required for these systems, particularly for battery-powered devices. To meet these requirements, folding and interpolating ADC are widely used in embedded ADC for communications IC. This paper presents the design procedure of a 6-bit folding and interpolating analog-to-digital converter (ADC) operating at a conversion rate of 1 Gsamples/s while only dissipating 8 mW. Design challenges and potential solutions are presented and verified through an implementation of this ADC in 1.8 V 0.18 μm standard CMOS technology.

Keywords

CMOS integrated circuits; analogue-digital conversion; embedded systems; low-power electronics; 0.18 micron; 1.8 V; 8 mW; battery-powered devices; communications IC; deep-submicron CMOS design; flash/folding ADC; high speed embedded ADC; high-performance analog-to-digital converters; interpolating ADC; low-power ADC; low-voltage constraints; mobile applications; Analog-digital conversion; Application software; Bandwidth; CMOS technology; Design engineering; Embedded computing; Mobile communication; Mobile computing; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2004. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-8253-6

Type

conf

DOI

10.1109/CCECE.2004.1349722

Filename

1349722