DocumentCode :
170678
Title :
A compilation flow for parametric dataflow: Programming model, scheduling, and application to heterogeneous MPSoC
Author :
Dardaillon, Mickael ; Marquet, Kevin ; Risset, Tanguy ; Martin, J. ; Charles, Henri-Pierre
Author_Institution :
INSA-Lyon, Univ. de Lyon, Villeurbanne, France
fYear :
2014
fDate :
12-17 Oct. 2014
Firstpage :
1
Lastpage :
10
Abstract :
Efficient programming of signal processing applications on embedded systems is a complex problem. High level models such as Synchronous dataflow (SDF) have been privileged candidates for dealing with this complexity. These models permit to express inherent application parallelism, as well as analysis for both verification and optimization. Parametric dataflow models aim at providing sufficient dynamicity to model new applications, while at the same time maintaining the high level of analyzability needed for efficient real life implementations. This paper presents a new compilation flow that targets parametric dataflows. Built on the LLVM compiler infrastructure, it offers an actor based C++ programming model to describe parametric graphs, a compilation front-end providing graph analysis features, and a retargetable back-end to map the application on real hardware. This paper gives an overview of this flow, with a specific focus on scheduling. The crucial gap between dataflow models and real hardware on which actor firing is not atomic, as well as the consequences on FIFOs sizing and execution pipelining are taken into account. The experimental results illustrate our compilation flow applied to compilation of 3GPP LTE-Advanced demodulation on a heterogeneous MPSoC with distributed scheduling features. This achieves performances similar to time-consuming hand made optimizations.
Keywords :
C++ language; data flow computing; graph theory; multiprocessing systems; optimisation; processor scheduling; program compilers; system-on-chip; 3GPP LTE-advanced demodulation; C++ programming model; FIFOs sizing; LLVM compiler infrastructure; SDF; application parallelism; compilation flow; compilation front-end; distributed scheduling features; embedded systems; execution pipelining; graph analysis features; heterogeneous MPSoC; high level models; optimization; parametric dataflow models; parametric graphs; signal processing applications; synchronous dataflow; verification; Computational modeling; Hardware; Program processors; Programming; Schedules; Synchronization; System-on-chip; compiler; data flow; heterogeneous MP-SoC; programming model; scheduling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2014 International Conference on
Conference_Location :
Jaypee Greens
Type :
conf
DOI :
10.1145/2656106.2656110
Filename :
6972461
Link To Document :
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