Title :
A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS
Author :
Chang-Yuan Liou ; Chih-Cheng Hsieh
Author_Institution :
Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
In this paper, a 10b 0.5-to-4MS/s asynchronous SAR ADC is proposed and prototyped in 90nm CMOS. The supply voltage is scaled down appropriately (0.4 to 0.7V) for different speeds to minimize power consumption of SAR control and switching energy. Moreover, a charge average switching (CAS) DAC is developed to reduce the switching energy of the DAC without an extra voltage reference and common-mode shift. In near-threshold operation with a scaled-down supply, a double-boosted sample-and-hold (S/H) circuit and a local-boosted switch are implemented for the linearity and accuracy requirements of the 10b ADC.
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital-analogue conversion; low-power electronics; sample and hold circuits; CAS DAC; CMOS; SAR control; asynchronous SAR ADC; charge average switching DAC; charge-average switching DAC; double-boosted sample-and-hold circuit; local-boosted switch; near-threshold operation; power consumption minimisation; scaled-down supply; size 90 nm; switching energy reduction; voltage 0.4 V to 0.7 V; CMOS integrated circuits; Capacitors; Partial discharges; Power demand; Solid state circuits; Switches;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487735
