A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS

In this paper, a 10b 0.5-to-4MS/s asynchronous SAR ADC is proposed and prototyped in 90nm CMOS. The supply voltage is scaled down appropriately (0.4 to 0.7V) for different speeds to minimize power consumption of SAR control and switching energy. Moreover, a charge average switching (CAS) DAC is developed to reduce the switching energy of the DAC without an extra voltage reference and common-mode shift. In near-threshold operation with a scaled-down supply, a double-boosted sample-and-hold (S/H) circuit and a local-boosted switch are implemented for the linearity and accuracy requirements of the 10b ADC.