Reducing cache leakage energy for hybrid SPM-cache architectures

In this paper, we study how to reduce the cache leakage energy efficiently in a hybrid SPM (Scratch-Pad Memory) and cache architecture. Since SPM can reduce the access frequency to the cache, we find it is possible to place the cache lines of the hybrid SPM-cache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without significant performance degradation. Also, we propose a Hybrid Drowsy-Gated Vdd (HDG) technique, which can adaptively exploit both short and long idle intervals to minimize leakage energy with insignificant performance overhead.