Architecture and Design Methodology for Structured LDPC Decoder

In this paper we propose a decoding architecture for turbo-like decoding algorithm of a particular class of Low-Density Parity Check codes. We define a methodology to design codes. In a first step a hardware architecture and the decoding scheduling are first selected. Then rules for the design of these codes are derived, aiming at improving the convergence of the decoding algorithm, while fitting with the proposed architecture. Last, performance results and details on the decoder implementation are provided to illustrate the interest of the approach.