DocumentCode
1707219
Title
0.5V 160-MHz 260uW all digital phase-locked loop
Author
Liu, Jen-Chieh ; Huang, Hong-Yi ; Yang, Wei-Bin ; Cheng, Kuo-Hsing
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Jhongli
fYear
2009
Firstpage
186
Lastpage
193
Abstract
A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The locking time of ADPLL is less then 32 reference clock cycles. The multiplication factor is 2 to 63. Power consumption is 260uW at 160-MHz and 80uW at 60-MHz with 0.5V supply voltage.
Keywords
CMOS digital integrated circuits; VHF oscillators; digital phase locked loops; phase locked oscillators; ADPLL locking time; ADPLL multiplication factor; ADPLL reference clock cycle; CMOS process; all-digital phase-locked loop; frequency 160 MHz; frequency 60 MHz; power 260 muW; power 80 muW; pulse-based digitally controlled oscillator; size 0.13 mum; voltage 0.5 V; Circuit optimization; Clocks; Counting circuits; Digital control; Energy consumption; Frequency; Jitter; Microprocessors; Phase locked loops; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on
Conference_Location
Liberec
Print_ISBN
978-1-4244-3341-4
Electronic_ISBN
978-1-4244-3340-7
Type
conf
DOI
10.1109/DDECS.2009.5012125
Filename
5012125
Link To Document