Title :
High-level symbolic simulation for automatic model extraction
Author :
Ouchet, Florent ; Borrione, Dominique ; Morin-Allory, Katell ; Pierre, Laurence
Author_Institution :
CNRS, UJF, Grenoble
Abstract :
This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types.
Keywords :
formal logic; hardware description languages; VHDL descriptions; VSYML; automatic model extraction; formal reasoning; high level symbolic simulation; Analytical models; Circuit simulation; Context modeling; Data mining; Indium phosphide; Laboratories; Numerical simulation; Robustness; Software design; Testing; Hardware design language; circuit simulation; simulation software;
Conference_Titel :
Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on
Conference_Location :
Liberec
Print_ISBN :
978-1-4244-3341-4
Electronic_ISBN :
978-1-4244-3340-7
DOI :
10.1109/DDECS.2009.5012132
