An overview of low-voltage VCO delay cells and a worst-case analysis of supply noise sensitivity

Author

Ei-Hage, M. ; Yuan, Fei

Author_Institution

Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont., Canada

Volume

3

fYear

2004

Firstpage

1785

Abstract

This paper presents a comparative study of the architecture and timing jitter of the delay-cells of low-voltage CMOS ring-VCOs. Design considerations, such as noise, single-ended versus differential, linearity and symmetry of load, and the output voltage swing of delay cells are examined in detail. The worst-case sensitivity of the delay time of the delay cells and that of the oscillation frequency of corresponding ring-VCO implemented in TSMC 0.18 μm CMOS technology are analyzed using Cadence´s Spectre with BSIM3v3 device models. Simulation results are presented.

Keywords

CMOS integrated circuits; circuit simulation; delay circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; low-power electronics; power supply circuits; sensitivity analysis; timing jitter; voltage-controlled oscillators; 0.18 micron; Cadence Spectre BSIM3v3 device models; TSMC CMOS technology; delay time; delay-cell architecture; design considerations; differential design; load linearity; load symmetry; low-voltage CMOS ring-VCO; low-voltage VCO delay cells; noise; oscillation frequency; output voltage swing; simulation; single-ended design; supply noise sensitivity; timing jitter; worst-case analysis; worst-case sensitivity; 1f noise; Circuit noise; Delay effects; Frequency; Low-frequency noise; Phase noise; Ring oscillators; Timing jitter; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2004. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-8253-6

Type

conf

DOI

10.1109/CCECE.2004.1349762

Filename

1349762