An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme

For chip-to-chip parallel interfaces, maintaining low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation of clock and data jitter [1]. Clock-recovery circuits consume a large portion of the I/O power. PLL/DLLs with a phase interpolator are widely used for the clock recovery circuits. However, they dissipate high power and jitter-tracking bandwidth (JTB) is low (PLL) or high (DLL), degrading the jitter correlation between data and clock. Recently, injection-locked oscillators (ILOs) have drawn much attention for the clock-recovery circuit of the FC interfaces due to their low power consumption [3-6]. By de-tuning the free-running frequency of an ILO, clock deskew can be performed and multiphase clocks can be generated without an additional multiphase generator. Also, ILOs can provide JTB of several hundred MHz, which is optimal for the FC interfaces in terms of the jitter correlation and BER [5].