Title :
A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS
Author :
Bhardwaj, Kshitij ; Narayan, S. ; Shumarayev, S. ; Lee, Taewoo
Author_Institution :
Stanford Univ., Stanford, CA, USA
Abstract :
Generating quadrature phases at low area and power overhead from a two-phase clock without frequency conversion is desirable for half-rate CDR architectures. This is useful for both embedded and forwarded clock systems, where quadrature generation by dividers, ring oscillators or coupled LC-VCOs is common. For example, [1] uses LC-VCOs followed by 2:1 dividers to generate the half-rate clocks for both TX and RX in a 28Gb/s transceiver. However, such an approach tends to be power- and area-inefficient for multi-lane implementations at data rates of 25Gb/s and beyond.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; transceivers; voltage-controlled oscillators; CEI short-reach CDR; CMOS; coupled LC-VCO; divider; embedded clock system; forwarded clock system; multilane implementation; phase-tunable quadrature-generation method; power 3.1 mW; quadrature generation; quadrature phase generation; ring oscillator; size 28 nm; transceiver; two-phase clock; Bit error rate; CMOS integrated circuits; Calibration; Clocks; Jitter; Receivers; Resonant frequency;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487793
