CESAME: a test chip for the validation of a parasitic emission prediction flow in 0.18 μm CMOS technology

Author

Vrigno, Bertrand ; Bendhia, S. ; Courau, L. ; Sicar, E.

Author_Institution

Central R&D, STMicroelectronics, Crolles, France

Volume

2

fYear

2004

Firstpage

372

Abstract

Due to increasing speed and complexity, integrated circuits (ICs) are faced with severe parasitic emission problems. The internal current switching, of the order of several amperes per nanosecond, provokes important voltage drops and ringing effects on the supply lines of the IC. This noise provokes conducted emission on the external supply lines as well as radiated emission over the surface of the circuit. In order to establish in the IC design flow an evaluation of the parasitic emission, an experimental circuit has been designed in CMOS 0.18 μm. The simulated and measured core noise are compared.

Keywords

CMOS digital integrated circuits; electromagnetic compatibility; electromagnetic interference; integrated circuit design; integrated circuit noise; prediction theory; 0.18 micron; CMOS technology; EMC; IC design flow; conducted emission; core noise; experimental circuit; integrated circuit complexity; internal current switching; parasitic emission prediction validation; supply line ringing effects; test chip; voltage drops; CMOS analog integrated circuits; CMOS integrated circuits; CMOS technology; Circuit testing; Current measurement; Electromagnetic interference; Electromagnetic measurements; Integrated circuit measurements; Integrated circuit noise; Noise measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility, 2004. EMC 2004. 2004 InternationalSymposium on

Print_ISBN

0-7803-8443-1

Type

conf

DOI

10.1109/ISEMC.2004.1349818

Filename

1349818