Title :
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits
Author :
Fuketa, Hiroshi ; Nomura, M. ; Takamiya, Makoto ; Sakurai, Takayasu
Author_Institution :
Univ. of Tokyo, Tokyo, Japan
Abstract :
In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (VDD) are required, as energy consumption is proportional to CVDD2. Near-threshold (Vt) operation achieves an energy minimum. Resonant clocking can reduce the effective capacitance of the clock distribution network. In this work, a new resonant clocking scheme enabling power reduction at any clock frequency is proposed and applied to a 0.37V 980kHz near-Vt logic circuit in 40nm CMOS.
Keywords :
CMOS integrated circuits; clock distribution networks; logic circuits; low-power electronics; power supply circuits; CMOS integrated circuit; capacitance reductions; clock distribution network; clock frequency; energy consumption; frequency 980 kHz; intermittent resonant clocking; near-threshold logic circuits; power reduction; power supply voltage; size 40 nm; voltage 0.37 V; Adders; Clocks; Logic circuits; Logic gates; Resistance; Resonant frequency; Timing;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-4515-6
DOI :
10.1109/ISSCC.2013.6487804
