A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth

Current-steering DACs are generally used in high-speed signal generation. The critical challenges for DACs are to realize the highest-possible spurious-free dynamic range (SFDR) and inter-modulation distortion (IMD) at the widest possible signal bandwidth. However, the above performances are degraded by many nonlinear causes, e.g., parasitic capacitor-induced finite output impedance [1], current-source (CS) mismatch, and input-code dependent switching transients [2]. While CS mismatch and input-code dependent switching transients result in distortion tones, the parasitic capacitor-induced finite output impedance further limits the high-linearity bandwidth and causes the SFDR to drop at high signal frequencies. In addition, low power consumption and small area are important factors for low-power applications and reduced implementation cost, respectively.