Title :
An efficient architecture of encoder and decoder for DisplayPort physical layer
Author :
Kim, Yongtae ; Song, Junyoung ; Heo, Woonhyung ; Kim, Chulwoo
Author_Institution :
Adv. Integrated Syst. Lab., Korea Univ., Seoul
Abstract :
This paper presents an efficient architecture of encoder and decoder for displayport. The proposed architecture provides high-speed and low-complexity for the hardware specified by the displayport standard. Moreover, the encoder and decoder require gate counts of only 0.94 K and 0.89 K, respectively.
Keywords :
decoding; display instrumentation; encoding; peripheral interfaces; decoder gate count; displayport physical layer; displayport standard hardware specification; encoder; Clocks; Computer buffers; Counting circuits; Decoding; Detectors; Hardware; Multiplexing; Physical layer; Strontium; Transmitters;
Conference_Titel :
Consumer Electronics, 2009. ICCE '09. Digest of Technical Papers International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-4701-5
Electronic_ISBN :
978-1-4244-2559-4
DOI :
10.1109/ICCE.2009.5012215
