DocumentCode
1709772
Title
The applicaiton of calculus on runtime verification
Author
Xie, Ruiyun ; Hai, Benzhai ; Guo, Zuhua ; Shao, Mingzhu
Author_Institution
Dept. of Comput. Sci. &Technol., Henan Mech. & Electr. Eng. Coll., Xinxiang, China
Volume
2
fYear
2010
Abstract
In this paper, a uniform calculus-based approach for synthesizing monitors checking correctness properties specified by a large variety of logics at runtime is provided, including future and past time logics, interval logics, state machine and parameterized temporal logics. We present a calculus mechanism to synthesize monitors from the logical specification for the incremental analysis of execution traces during test and real run. The monitor detects both good and bad prefix of a particular kind, namely those that are informative for the property under investigation. We elaborate the procedure of calculus as monitors.
Keywords
calculus; finite state machines; program verification; supervisory programs; temporal logic; correctness checking; incremental analysis; logical specification; runtime verification; state machine; synthesizing monitor; uniform calculus based approach; Calculus; Computer science; Construction industry; Monitoring; Runtime; Semantics; Transforms; Calculus; Runtime Verification; synthesizing monitors;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing Systems (ICSPS), 2010 2nd International Conference on
Conference_Location
Dalian
Print_ISBN
978-1-4244-6892-8
Electronic_ISBN
978-1-4244-6893-5
Type
conf
DOI
10.1109/ICSPS.2010.5555288
Filename
5555288
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