Energy optimization in a Network-on-Chip with dynamically reconfigurable processing nodes

Author

Nunez-Yanez, J.L. ; Hosseinabady, M. ; Nabina, A. ; Zaidi, I.

Author_Institution

Dept. of Electron. Eng., Bristol Univ., Bristol, UK

fYear

2009

Firstpage

308

Lastpage

313

Abstract

This work investigates how the dynamic reconfiguration features available in modern FPGAs can be combined with a voltage-frequency scaling strategy to adapt the processing performance available in the system to the available energy budget. As defined by a hardware operating system, each processing node can configure itself as a virtual processor able to execute a control algorithm that will adjust the voltage-frequency operational point of the reconfigurable fabric so that functions mapped to this fabric meet their processing deadlines. Once the new operational point has been reached the processor is removed from the fabric. This is then reconfigured to implement the application-specific logic exploiting the dynamic nature of FPGAs.

Keywords

field programmable gate arrays; integrated logic circuits; network-on-chip; operating systems (computers); optimisation; power aware computing; reconfigurable architectures; FPGA; application-specific logic; dynamically reconfigurable processing nodes; energy optimization; hardware operating system; network-on-chip; virtual processor; voltage-frequency scaling strategy; Computer networks; Control systems; Dynamic voltage scaling; Fabrics; Field programmable gate arrays; Hardware; Network-on-a-chip; Reconfigurable logic; Silicon; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Control Applications, (CCA) & Intelligent Control, (ISIC), 2009 IEEE

Conference_Location

St. Petersburg

Print_ISBN

978-1-4244-4601-8

Electronic_ISBN

978-1-4244-4602-5

Type

conf

DOI

10.1109/CCA.2009.5281128

Filename

5281128