Title :
SOC verification infrastructure
Author :
Vladimir, Hahanov ; Eugenia, Litvinova ; Irina, Pobezhenko
Author_Institution :
Comput. Eng. Fac., Kharkov Nat. Univ. of Radioelectron., Kharkov, Ukraine
Abstract :
The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
Keywords :
hardware description languages; logic design; system-on-chip; SOC verification infrastructure; digital systems; logical structure HDL-program; simulation environment; system HDL models; testable analysis; testing technology; verification technology; Analytical models; Controllability; Engines; Observability; Registers; Software; Testing;
Conference_Titel :
Computational Technologies in Electrical and Electronics Engineering (SIBIRCON), 2010 IEEE Region 8 International Conference on
Conference_Location :
Listvyanka
Print_ISBN :
978-1-4244-7625-1
DOI :
10.1109/SIBIRCON.2010.5555318
