A 5-level discrete-time power encoder with measured coding efficiency of 70% for 20-MHz LTE digital transmitter

This paper reports the recent development on power coding method of generating a 5-level intermediate frequency PWM-based high speed digital-RF bit train, which is used as the input switching signal for class-S digital RF power amplifiers in the digital transmitter. By introducing the discrete-time power coding process at an IF of around 60 MHz, digital transmitter at cellular bands then becomes feasible to implement with current FPGA technologies. It can lower the required sampling rate more than 10 times compared with RF carrier PWM. In addition, a linearizer is designed using a look-up-table to minimize the nonlinear coding effects of the power encoder. The demonstrator shows the state-of-the-art measured power coding efficiency of 70.47% and SNR>30dB for a 20 MHz LTE signals with PAPR of 10.25 dB at 1.9 GHz with our proposed approach.