DocumentCode :
1710691
Title :
High performance photo-sensitive insulating materials for high density multi-layer wiring boards
Author :
Morishima, Makoto ; Akahoshi, Haruo ; Kawamoto, Mineo ; Suwa, Tokihito ; Miyazaki, Masashi ; Fukai, Hiroyuki
Author_Institution :
Res. Lab., Hitachi Ltd., Ibaraki, Japan
fYear :
1998
Firstpage :
68
Lastpage :
71
Abstract :
The photo-via build-up process is a most significant candidate for fabrication of high density multi-layer wiring boards for high density packaging using CSP and flip-chip direct attach. We have developed a new type of photo-sensitive dielectric. The dielectric delivers high resolution in fabrication of photoformed microvia holes with an aspect ratio of 1.0. The photo-sensitive dielectric showed excellent electrical and mechanical properties for surface mounted wiring boards. It also shows outstanding mechanical properties, especially in the high temperature region. Excellent insulating properties and adhesion were proven, even after pressure cooker test (PCT) conditions. These features offer a great advantage in achieving higher interconnect reliability in direct-chip attachment on low cost multichip modules using sequential build-up substrates
Keywords :
adhesion; chip scale packaging; circuit reliability; dielectric thin films; flip-chip devices; image resolution; integrated circuit interconnections; laminates; microassembling; multichip modules; photolithography; printed circuit testing; printed circuits; surface mount technology; CSP; adhesion; dielectric resolution; direct-chip attachment; electrical properties; flip-chip direct attach; high density multi-layer wiring boards; high density packaging; high temperature properties; insulating properties; interconnect reliability; mechanical properties; microvia hole aspect ratio; multichip modules; photo-sensitive dielectric; photo-sensitive insulating materials; photo-via build-up process; photoformed microvia holes; pressure cooker test; sequential build-up substrates; surface mounted wiring boards; Adhesives; Chip scale packaging; Costs; Dielectric materials; Dielectrics and electrical insulation; Fabrication; Mechanical factors; Temperature; Testing; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
IEMT/IMC Symposium, 2nd 1998
Conference_Location :
Tokyo
Print_ISBN :
0-7803-5090-1
Type :
conf
DOI :
10.1109/IEMTIM.1998.704522
Filename :
704522
Link To Document :
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