Fast/area efficient 8-bit A/D and D/A designs in 0.8 μm cmos technology using layout generators

Author

Balakrishan, V.G. ; Ramaswamy, Sridhar ; Siferd, Raymond E.

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

Volume

1

fYear

1997

Firstpage

372

Abstract

High performance 8-bit analog-to-digital (A/D) and digital-to-analog (D/A) converters are presented here. To realize the DAC, the advantages of voltage scaling and charge scaling techniques have been combined. For the ADC, a two step “ripple through” A/D architecture which achieves high conversion speeds and area efficiency is presented. Both the A/D and D/A designs were realized using the Mentor Graphics Generator Design Tools (GDT)

Keywords

CMOS integrated circuits; SPICE; VLSI; analogue-digital conversion; circuit layout CAD; digital-analogue conversion; integrated circuit layout; 0.8 mum; A/D; CMOS technology; D/A design; Hspice; Mentor Graphics Generator Design Tools; VLSI; analog-to-digital converters; area efficiency; charge scaling; digital-to-analog converters; ripple through architecture; voltage scaling; CMOS technology; Capacitance; Capacitors; Circuits; Digital signal processing; Gas discharge devices; Graphics; Resistors; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1997. NAECON 1997., Proceedings of the IEEE 1997 National

Conference_Location

Dayton, OH

Print_ISBN

0-7803-3725-5

Type

conf

DOI

10.1109/NAECON.1997.618107

Filename

618107