Special purpose processor speeds up DSP functions

Author

Landers, George

Author_Institution

Infinite Technol. Corp., USA

fYear

1996

Firstpage

201

Lastpage

204

Abstract

A new class of arithmetic datapath processors are available in either device or embedded form. These reconfigurable arithmetic datapath (RADTM) devices offer reconfigurablilty of FPGAs with the performance of algorithm specific silicon designs. The heart of the RAD architecture is a MacroSequencer. By programming the MacroSequencer to a specific algorithm, the hardware configures itself to that algorithm. Operations are performed concurrently in the pipelined structure. All programming, short term data storage and coefficients are stored within the MacroSequencer. The RAD MacroSequencer may be reconfigured to a new algorithm in as little as 25 ms. The RAD architecture is particularly suited to accelerating the performance of data stream algorithms

Keywords

digital arithmetic; digital signal processing chips; field programmable gate arrays; DSP functions; FPGAs; MacroSequencer; algorithm specific silicon designs; arithmetic datapath processors; data stream algorithms; reconfigurable arithmetic datapath devices; short term data storage; special purpose processor; Algorithm design and analysis; Clocks; Counting circuits; Data buses; Digital signal processing; Finite impulse response filter; Fixed-point arithmetic; Hardware; Read-write memory; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

ELECTRO '96. Professional Program. Proceedings.

Conference_Location

Somerset, NJ

Print_ISBN

0-7803-3271-7

Type

conf

DOI

10.1109/ELECTR.1996.501227

Filename

501227