Title :
Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology
Author :
Cho, Dac-Hyung ; Seung, Man-Ho ; Kim, Nam-Ho ; Park, Hun-Sup ; Wee, Jac-Kyung ; Park, Young-June ; Min, Hong-Shik
Author_Institution :
Adv. Device Phys. Lab., Hyundai Electron. Ind. Co., Kyungki, South Korea
Abstract :
This paper presents the measurement and characterization of multi-layered interconnect capacitances for a 0.35 μm CMOS logic technology, which is becoming a critical circuit limitation to high performance VLSI design. To measure multi-layered capacitances of interconnect lines, test structures and the measurement methodology are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies
Keywords :
CMOS integrated circuits; CMOS logic circuits; VLSI; capacitance measurement; integrated circuit interconnections; integrated circuit measurement; integrated circuit testing; 0.35 micron; CMOS logic technology; TCAD tools calibration; characterization; deep submicron VLSI technology; high performance VLSI design; high-speed interconnect technologies; measurement methodology; multi-layered interconnect capacitance; test structures; CMOS logic circuits; CMOS technology; Capacitance measurement; Chemical technology; Circuit testing; Coupling circuits; Electric variables measurement; Integrated circuit interconnections; Planarization; Very large scale integration;
Conference_Titel :
Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3243-1
DOI :
10.1109/ICMTS.1997.589346
