DocumentCode
1711865
Title
Bandwidth reduced H.264/AVC hardware design with various windows of lossless compressor and cache scheme
Author
Park, Chan-Sik
Author_Institution
Digital Media R&D center, Samsung Electron. Co., Suwon
fYear
2009
Firstpage
1
Lastpage
2
Abstract
The bus bandwidth insufficiency and the real-time processing of H.264/AVC are the most serious problems in High Definition (HD) or Ultra Definition (UD) video data. This paper presents the bandwidth reduced architecture to solve these problems. By using various windows of lossless compressor and cache scheme with each controller, we can significantly reduce both data bandwidth and processing cycles.
Keywords
cache storage; controllers; data compression; motion compensation; video coding; H.264-AVC hardware design; bandwidth reduced architecture; bus bandwidth; cache scheme; controller; high-definition video data; lossless compressor; ultradefinition video data; Automatic voltage control; Bandwidth; Filters; Hardware; High definition video; Motion control; Motion estimation; Pipelines; Quantization; Video compression; Bus bandwidth insufficiency; HD; UD; cache scheme; lossless compressor; real-time processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2009. ICCE '09. Digest of Technical Papers International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
978-1-4244-4701-5
Electronic_ISBN
978-1-4244-2559-4
Type
conf
DOI
10.1109/ICCE.2009.5012302
Filename
5012302
Link To Document