Modeling, design and automation of 5 Gbps serial link transceiver with jitter cancellation

In this paper, a generic high speed link transceiver is modeled, and this model is used to obtain high level design parameters for the design. With system level design inputs, the model is further developed to obtain optimum circuit level design parameters and other design level decisions for a given signal integrity specification. The model is developed using Algorithmic Modeling Interface (AMI), and design parameters for USB3.0 is obtained and USB3.0 transceiver is designed. The transceiver implemented in CMOS 90nm technology is discussed, and the results are compared with the model´s predicted results (thus validating the model). For USB3.0, a two tap FFE and a 3-tap DFE is found optimum and then circuit level design is implemented. This circuit-level implementation from the parameters obtained can be automated, thereby automating full design flow from specification to circuit. This automated flow to meet the given signal integrity specifications is discussed.