Using device simulations to optimize ESD protection circuits

As integrated circuits are getting more and more complex, they are becoming increasingly vulnerable to transient disturbances (e.g. to electrostatic discharges, ESD). The development approaches for on-chip ESD protection devices often have a very experimental character: ESD designers make use of trial-and-error procedures to evaluate many variations of protection structures. This methodology is very time-consuming, as it can require several redesigns to find proper ESD protection devices for a given process technology. Also, from one process generation to the next, already well-established ESD structures may completely change their ESD behavior. Now, more sophisticated design approaches make use of TCAD-based techniques. Simulations of ESD circuits provide a deeper understanding of the functionality of their protection behavior. In this paper we show how such simulation techniques have been successfully used to design an efficient trigger-circuit for SCR, a specific class of very powerful ESD protection devices.