An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips

Author

Jara-Berrocal, Abelardo ; Gordon-Ross, Ann

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA

fYear

2011

Firstpage

219

Lastpage

222

Abstract

Partial reconfiguration (PR) enhances traditional FPGA-based system-on-chips (SoCs) by providing additional benefits such as reduced area and increased functionality as compared to non-PR SoCs. However, since leveraging these additional benefits requires specific designer expertise and increased development time, PR has not yet gained widespread usage. In this paper, we present an integrated development toolset that automates the implementation of PR SoCs on FPGA devices and leverage this tool in a rapid design space exploration case study.

Keywords

field programmable gate arrays; integrated circuit design; reconfigurable architectures; system-on-chip; FPGA-based system-on-chips; SoC; design space exploration; implementation methodology; integrated development toolset; partially reconfigurable system-on-chips; Clocks; Computer architecture; Field programmable gate arrays; Hardware; Runtime; Software; System-on-a-chip; partial reconfiguration; reconfigurable computing; system-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors (ASAP), 2011 IEEE International Conference on

Conference_Location

Santa Monica, CA

ISSN

2160-0511

Print_ISBN

978-1-4577-1291-3

Electronic_ISBN

2160-0511

Type

conf

DOI

10.1109/ASAP.2011.6043272

Filename

6043272