A 0.5 V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes

This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses an over-V_CC grounded data storage (OVGS) scheme. The key target of OVGS is to minimize the charge amount supplied from the embedded charge pump circuits, which are required to boost the effective gate to source voltage (V₀=V _GS-V_T) up to 0.8 V necessary to achieve 100 MHz-operation even at 0.5 V single power-supply. Thus, the key low-power strategy of OVGS is “putting the right (higher efficiency) boosted power-supply from the charge pump circuit into the right position in the SRAM cell”. This paper focuses on why OVGS can realize a greater saving of the charge amount supplied from the boosted power-line and can reduce the power dissipation to ⩽1/30.4 and ⩽1/3.9 compared to the previously reported negative source drive (NSD) scheme (Mizuno et al., 1995) and negative word-line drive (NWD) scheme (Itoh et al., 1996), respectively, while achieving a 0.5 V/100 MHz-operation