Title :
Switching activity analysis for sequential circuits using Boolean approximation method
Author :
Uchino, Taku ; Minami, Fumihiro ; Murakata, Masami ; Mitsuhashi, Takashi
Author_Institution :
Semicond. DA & Test Eng. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
We propose an incremental probabilistic approach to calculate the signal probabilities and switching activities of the internal nodes of sequential logic circuits. Spatio-temporal correlations are fully considered by using Multi-Terminal Binary Decision Diagrams (MTBDD) with real number valued terminals. The running time of our approach is short because the depth of the MTBDD does not depend on circuit size but only on the user-specified unrolling number, which is usually 2 or 3. Experimental results show that our approach is 100-times faster than logic simulation and 10-times more accurate than the previous approach which ignores all correlations
Keywords :
Boolean functions; CMOS logic circuits; correlation methods; probability; sequential circuits; Boolean approximation method; CMOS VLSI; incremental probabilistic approach; internal nodes; multi-terminal binary decision diagrams; real number valued terminals; sequential circuits; signal probabilities; spatio-temporal correlations; switching activity analysis; unrolling number; zero-delay model; Approximation methods; Boolean functions; Circuit analysis; Circuit testing; Data structures; Logic circuits; Magnesium compounds; Probability; Sequential circuits; Switching circuits;
Conference_Titel :
Low Power Electronics and Design, 1996., International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-3571-6
DOI :
10.1109/LPE.1996.542734
