A phase detection scheme for clock and data recovery applications

This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing six levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang phase detectors, a scheme of phase delay sensing is proposed that eliminates the need to sample the data stream close to data transitions in the locked state. Behavioural simulations are provided comparing the performance of the proposed phase detector with that of a conventional bang-bang phase detector.