Very low charge injection switched-current memory cell

A new switched-current memory cell is proposed which achieves very low charge injection errors. The technique virtually eliminates the signal-dependent error, leaving only an offset which is cancelled using either dummy switches or a fully differential configuration. The improved memory cell was designed using a standard 3.3 V, 0.8 μm CMOS digital process. Simulation results demonstrate that the signal-dependent charge injection error is lowered by as much as two orders of magnitude