Title :
Solder joint reliability model vath modified Darveaux´s equations for the micro smd wafer level-chip scale package family
Author :
Zhang, L. ; Sitaraman, R. ; Patwardhan, V. ; Nguyen, L. ; Kelka, N.
Author_Institution :
National Semiconductor Corporation
Keywords :
Chip scale packaging; Electronic packaging thermal management; Electronics packaging; Equations; Fatigue; Semiconductor device modeling; Semiconductor device packaging; Soldering; Testing; Wafer scale integration;
Conference_Titel :
Electronic Components and Technology Conference, 2003. Proceedings. 53rd
Print_ISBN :
0-7803-7791-5
DOI :
10.1109/ECTC.2003.1216338
