A scale-space chip

Author

Ranganathan, N. ; Shah, Mubarak

Author_Institution

Dept. of Comput. Sci., Central Florida Univ., Orlando, FL, USA

fYear

1988

Firstpage

420

Abstract

Scale-space is a representation for detecting and organising intensity changes that occur at various scales in an image. A single-chip VLSI design is proposed for scale-space computation in one and two dimensions. The architecture of the chip is based on an algorithm that can provide speeds that are an order of magnitude higher than the speeds obtainable from the other systems proposed in the literature. The design uses the principles of modularity, expandability and parallelism, and fully utilizes the three properties of the Gaussian: symmetry, separability, and scaling. The proposed algorithm and the hardware architecture use a very high degree of pipelining and parallelism. The chip can be implemented in either nMOS or CMOS technology

Keywords

MOS integrated circuits; VLSI; computer vision; computerised pattern recognition; computerised picture processing; integrated circuit technology; microprocessor chips; parallel architectures; pipeline processing; CMOS technology; chip architectures; computer vision; expandability; image intensity change detection; intensity change organisation; modularity; nMOS technology; parallelism; pattern recognition; picture processing; pipelining; scale-space chip; separability; single-chip VLSI design; symmetry; Computational efficiency; Computer architecture; Computer science; Computer vision; Laplace equations; Layout; Organizing; Parallel processing; Power generation; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Pattern Recognition, 1988., 9th International Conference on

Conference_Location

Rome

Print_ISBN

0-8186-0878-1

Type

conf

DOI

10.1109/ICPR.1988.28257

Filename

28257