FAST: FPGA targeted RTL structure synthesis technique

Presents an approach for mapping RTL structures onto FPGAs. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Each component part consists of single-bit or multi-bit slice of one or more closely connected RTL components and is realized using one or more CLBs. For this mapping onto CLBs, primarily function decomposition is employed. Conditions for some decompositions, disjunctive as well as nondisjunctive, useful in the FPGA context have been derived. As decomposition is a computation intensive process, some necessary conditions which are simple to check and eliminate a large percentage of trial partitions have been evolved